1. Field of the Invention
The present invention relates to PWM power regulators, and more particularly to a method of detecting phase body diode using an auto-zero comparator in a synchronous rectified MOSFET driver.
2. Description of the Related Art
A synchronous rectified field-effect transistor (FET) driver for a power regular includes two switching FETs coupled in series between an input voltage signal and ground at an intermediate phase node. An output inductor has one end coupled to the phase node and its other end coupled to a load. A pulse-width modulation (PWM) feedback circuit toggles activation of the switching FETs to regulate power supplied to the load. PWM logic is responsive to a PWM signal having two logic states indicative of the phases of each PWM cycle. The upper FET is turned on while the lower FET is turned off during one phase of each PWM cycle, and then the upper FET is turned off and the lower FET turned on during the remaining phase of the PWM cycle. Operation toggles in this manner while the PWM control circuit regulates the PWM duty cycle to control power delivered to the load.
Shoot-through protection is designed primarily for preventing premature activation of one of the FETs. Simultaneous activation of both FETs results in significant efficiency degradation and possible damage to the system. Shoot-through protection designs require a fast loop response from the time of detection to the time of FET activation. It is desired that the dead time of both phase edges of each PWM cycle be minimized to improve or otherwise maximize power conversion efficiency. An important dead time to consider is when the body diode of the lower FET starts to conduct indicating that the lower FET is in the off state. Body diode detection is challenging due to phase node variability mainly effected by the voltage drop when the FET is in the on state and the natural oscillation caused by immediate turn off of the FET. In an attempt to reduce dead time, premature detection causes a false detection and late detection increases dead time.
The voltage of the PHASE node is a by-product of the RDSON of the lower FET and the load current on the converter. For example, an RDSON of 5 milliohms and a 20 Ampere (A) load gives a PHASE node voltage drop of approximately 100 millivolts (mV) below ground, or −100 mV. The RDSON may vary depending upon the FET and varies with temperature. Temperature and current load, among other variables, causes changes of the PHASE node voltage from cycle to cycle and over time. Such variables have made it difficult to determine when the lower FET is off and when the upper FET should be activated. In some conventional configurations, the lower FET gate drive signal, referred to as LGATE, was monitored in an attempt to determine when the lower FET was off. In particular, when the LGATE fell to a predetermined voltage level, such as 1.5 Volts (V), it was assumed that the lower FET was off and that the upper FET could be turned on. This solution was somewhat unreliable and inconsistent. The temperature, load and other variables resulted in significant variations from one cycle to the next or over time resulting in unpredictable results and significant inefficiencies. Oftentimes the dead time from when the lower FET is turned off to activation of the upper FET was large significantly degrading efficiency. It is desired to identify the appropriate time to detect the body diode while preventing false triggering and without compromising dead time.